1. Field of the Invention
The invention relates to memory cells, in particular to volatile memory cells.
2. Description of the Related Art
When accessing a memory cell, an electric potential (hereinafter, potential) representing stored information may be superimposed by an additional potential caused by e.g. an accessing device. Thus, the potential representing the stored information may change, which may result in cell instability and, subsequently, in a loss of information, in particular when the memory cell comprises latches for storing information bits. Due to local process variations, an instability of e.g. SRAM (static random access memory) cells is a major factor reducing the yield for memory blocks at low voltage. The process variations further affect the writeability of a memory cell and its read current (for instance twice less yield loss, both cumulated). Thus, a possibility of instability of the cell reduces the access reliability.
In order to prevent cell instability and to increase access reliability, a dynamic VDD switching of the cell supply may be performed. During an access operation, e.g. during a read operation, the VDD at the memory cell is higher than a periphery VDD, whereas during a write operation the VDD at a selected column of the memory cell is switched back to the regular VDD in order to enable the write operation.
However, dynamic VDD switching of the cell supply suffers from the disadvantage that a further voltage supply is necessary in order to provide different VDD voltages.
The change of the potential representing the stored information may also occur when several devices simultaneously access the memory element for e.g. while reading out information from the memory element (dual access). Moreover, one of the access devices may prevent another access device from simultaneously accessing the memory cell due to e.g. an additional voltage (potential) caused by the access device. Therefore, the access reliability is reduced. Generally, two kinds of behaviors can then be distinguished. In the case of an instability, the stored value tends to be corrupted. In the case of a read unreliability, an access transistor suffers from the change of the potential of the storing node and the current or charge it is able to deliver to the bitline is reduced, which results in a degradation of read reliability since sensing margins are degraded.
Multi-port SRAM memories, especially Dual-Port SRAM memories, are however often employed in chip designs. The most risky operation occurs when, during e.g. a dual read operation, row addresses of memory elements are identical for both ports A and B at which the memory device is accessed via e.g. bitlines and wordlines WLA and WLB. In this case, both wordlines (WLA and WLB) of the same bit cell row are simultaneously selected. The reliability of a double read operation is degraded, especially at low voltage (e.g. 0.7 volt) for deep submicron technologies, especially if a threshold voltage is high when compared with the low voltage.
In order to increase the access reliability during a dual access operation, the memory cells may be changed which is associated with increased costs. Furthermore, the simultaneous access can be avoided by allowing an access device to access the memory element after another access device has completed the access operation. This results in an increased total assess time and reduced flexibility.
Since the known methods provide different solutions to increasing the access reliability for different access scenarios, different solutions have to be implemented for single and dual access operations which is associated with an increased complexity and with a reduced flexibility.